1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of forming conductor material patterns of capacitor electrodes and so on of semiconductor memory device.
2. Description of the Related Art
As semiconductor memory device permitting arbitrarily inputting and outputting the storage information, there is a DRAM. Each memory cell of this DRAM is formed of one transfer transistor and one capacitor. The DRAM has a simple structure, and is widely used as a device most suited for high integration of the semiconductor memory device.
In the field of the capacitors of such a memory cell, capacitors having a three-dimensional structure have been developed and put into practical use with further high integration of semiconductor devices. The three-dimensional structure of the capacitors is adopted for the following reasons. As semiconductor devices become finer in size and higher in density, it has become indispensable to reduce the area occupied by the capacitors. For ensuring the stable operation and reliability of the DRAM, however, capacitance values equivalent to at least a fixed value are needed. Therefore, it becomes necessary to change the electrode of each capacitor from a planar structure to a three-dimensional structure and thereby expand the surface area of the capacitor electrode within a reduced occupied area.
As the capacitor having a three-dimensional structure in each memory cell of the DRAM, there are a capacitor having a stack structure and a capacitor having a trench structure. Each of these structures has both merits and demerits. The capacitor of the stack structure is highly immune to incidence of alpha rays or noise from a circuit or the like, and operates stably even in the case where the capacitance value is relatively small. Therefore, it is considered that the capacitor of the stack structure is effective even in 4 gigabits for which the design standard of semiconductor devices becomes approximately 0.15 .mu.m.
In the case of the capacitor having the stack structure (hereafter referred to as stack type capacitor), however, a dielectric film (capacitive insulation film) having a very high dielectric constant is needed in order to ensure a predetermined capacitance value in a region having a minute area. As such a capacitive insulation film, materials each having a high dielectric constant such as SrTiO.sub.3 (hereafter referred to as STO film), (Ba, Sr)TiO.sub.3 (hereafter referred to as BST film), Pb(Zr, Ti)0.sub.3 are vigorously investigated. And as a lower electrode of the stack type capacitor, a new conductor material becomes necessary. This aims at ensuring high reliability of the capacitor by a suitable combination of the high dielectric constant material and the lower electrode. For example, as described in DIGEST OF TECHNICAL PAPERS of 1994 INTERNATIONAL ELECTRON DEVICES MEETING, pp. 831 to 834, SrTiO.sub.3 is used for the capacitive insulation film, and a conductor material of ruthenium dioxide (RuO.sub.2) is used for the lower electrode.
Hereafter, a conventional method for forming the capacitor will be described by referring to the drawing. FIGS. 1A to 1D are sectional views of the capacitor electrode of the above described stack type in the order of production process. FIGS. 2A and 2B are a schematic top view of the stack type capacitor and a sectional view thereof seen along a line I--I, respectively.
As shown in FIG. 1A, underlying insulation film 101 is formed on a semiconductor substrate such as a silicon substrate. On this underlying insulation film 101, a conductor film 102 made of RuO.sub.2 is formed by using the reactive sputtering method. The conductor film 102 is of a polycrystalline structure and has a columnar crystal structure. On the surface of the conductor film 102, therefore, surface jogs 103 of approximately 5 nm are formed.
Subsequently, on the conductor film 102 having the surface jogs 103, a SOG (Silicon on Glass) film 104 and a resist film 105 are formed as stacked layers as shown in FIG. 1B. The resist film 105 is patterned by using the photolithography technique. By using a resist film 107 thus patterned (FIG. 1C) as a mask, the SOG film 104 is subjected to dry etching.
In this way, a SOG film mask 106 is formed as shown in FIG. 1C. On the SOG film mask 106, the resist mask film 107 remains. The SOG film mask 106 has tapered side shapes.
In succession, the conductor film 102 is subjected to dry etching by using the SOG film mask 106 and the resist mask 107 as etching masks. As etching gas, a mixed gas of O.sub.2 and Cl.sub.2 is used.
In this way, a lower electrode 108 made of RuO.sub.2 is formed on the underlying insulation film 101 as shown in FIG. 1D. Thereafter, the SOG film 106 is removed.
In such a stack type capacitor having the lower electrode 108, a capacitive insulation film 110 is formed on the top face of the lower electrode 108, on the side faces of the electrode 109, and on the underlying insulation film 101 as shown in FIGS. 2A and 2B. This capacitive insulation film 110 is formed of, for example, a BST film or the like. And an upper electrode 111 is formed so as to cover the whole. On a predetermined region of the surface of a semiconductor substrate 112, a diffusion layer 113 is formed. On this semiconductor substrate 112, the above described underlying insulation film 101 is formed. The lower electrode 108 is connected to the diffusion layer 113 by a plug 114 obtained by forming an opening locally through the underlying insulation film 101 and burying a conductive material in this opening.
In the stack type capacitor having the lower electrode 108 made of RuO.sub.2, the surface jogs 103 are formed on the top face of the lower electrode 108. In addition, a large number of jogs are formed on electrode side faces 109 of the lower electrode 108 subjected to dry etching. In other words, the pattern shape of the lower electrode 108 is poor.
In the above described conventional technique, the pattern shape of the conductor film such as the lower electrode of the capacitor becomes very bad, and jogs occur in the pattern edge of the conductor film. This is because the conductor film is a polycrystalline film having a columnar structure and consequently jogs are formed on the surface. Because of jogs of the surface of the conductor film, the film thickness of an inorganic insulation film such as the SOG film for etching mask used in the processing of the conductor film becomes great. And the section of the inorganic insulation film mask such as the SOG film mask becomes tapered. In such a shape, the film thickness of the inorganic insulation film mask is made a difference on the pattern edges of the mask by the jogs of the surface of the underlying conductor film. Because of the dry etching of the conductor film using such an inorganic insulation film mask, the pattern shape becomes very bad. The jogs on the pattern edges depend upon the diameter of the polycrystalline particle of the conductor film. In other words, the greater the particle diameter, the greater the jogs. In the above described example of RuO.sub.2 of the conventional technique, such jogs amount to approximately 50 nm.
If the lower electrode having such a bad pattern shape is used in a stack type capacitor, the holding characteristic of the information charge stored in the capacitor becomes worse. This will now be described by referring to FIG. 3. In the graph diagram of FIG. 3, its abscissa indicates the leak current per unit area of the capacitor, and its ordinate indicates the accumulative ratio of 1,000 stack type capacitors. Here, the leak current represents a value in the case where 1 V is applied to the capacitor electrode.
As shown in FIG. 3, the ratio of the capacitor for which the leak current value is 10.sup.-7 A/cm.sup.2 or the like is approximately 5%. For the leak current of 10.sup.-6 A/cm.sup.2, the ratio becomes approximately 50%. And such a capacitor that the leak current becomes approximately 10.sup.-5 A/cm.sup.2 is also present. As the leak current thus becomes large, the holding time for storing the information charge decreases. This increase of the leak current of the capacitor is caused by concentration of the electric field on the pattern edge of the lower electrode and the jog portions of the side faces.
In the case of application to wiring and the like, such occurrence of the jogs on the pattern edges and so on of the conductor film makes it difficult to obtain finer wiring.